In a network switch system having a plurality of modules coupled to a bi-directional bus, one of the signals transmitted to bus interface circuits on each module is a clock signal used to control the timing of data transfer operations. This clock signal synchronizes the transmission and reception of data between physically separated points on the bus.
For proper operation of the system, clock signals should arrive at the bus interface circuitry at the same time; otherwise, reliable data transmission is not ensured. For example, if a bus interface circuit receiving data is "clocked" later than others, the earlier-clocked bus interface circuits may overwhelm the data before it is stored at its proper destination. This lack of simultaneity in reception of the clock signals, i.e., clock skew, directly increases the amount of time that the data must remain stable on the bus to ensure reliable data transmission; this, in turn, increases the time required for each data transfer on the bus and, thus reduces the speed of the bus.
The amount of clock skew introduced into a network switch system is a direct function of the variations and propagation delays among clock transmitter and receiver chips, and velocity factor differences in module etch of the system. A chip, i.e., a small, single piece of silicon on which integrated circuits are formed, typically comprises transistors. In digital logic applications, a transistor switches "on" when saturated and "off" when non-conducting to generate full "signal" swings between two power supply voltages. Propagation delay is affected by the switching speed of the transistor and is highly dependent upon variations in the fabrication process of the chip. In addition, the applied voltage, the operating temperature and the loading conditions of the chip effect its switching speed.
For logic switching applications, the transistors of a chip are typically configured as inverter and buffer circuits. An inverter inverts the logic sense of a binary signal; a buffer is used merely for signal amplification. That is, the buffer circuit does not produce any particular logic function since the binary value of the output is the same as the binary value of the input. However, buffering of low-level signals within semi-conductor chips to develop high-level digital pulse signals is very susceptible to propagation delay variations due to process, voltage, and temperature (PVT) variations. Differences in propagation delay between clock buffer chips in a system directly translate into skew. The magnitude of such skew is exacerbated when the clocking speed of the system (and, in particular, the switching speed of the transistors) increases.
The problem of clock skew in a high-speed clocking system is addressed partly by employing a central system clock source that generates and distributes clock signals to the respective modules over unidirectional clock lines. For example, clock generation circuits of the source preferably distribute the generated clock signals over identical trace lengths such that these signals arrive essentially simultaneously at the modules. In each module, the incoming clock signals are typically processed, e.g., shaped and amplified, before use by various components of the module. Such processing necessarily delays the signals; the delays can be expected to vary from module to module of the system because of PVT variations among the modules.
In addition, the topology of the clock distribution path located on each module can be expected to vary from module to module. These variations contribute significantly to clock skew and the present invention is directed to the reduction of that skew. More specifically, the present invention is directed to delivering low-skew, high-speed clock signals to points on the module where the clock signals are actually used, i.e., at their output buffers.